One of the main techniques for debugging power converters is hardware-in-the-loop (HIL),\nwhich is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common\ndesign platforms due to their acceleration capability. In this case, the widths of the signals have to be\ncarefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the\nbest options because although the design time is high, it allows the personalization of the number of\nbits in every signal. The representation of state variables in power converters has been previously\nstudied, however other signals, such as feedback signals, can also have a big influence because they\ntransmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of\nthe number of bits in the feedback signals of a boost converter, but the conclusions can be extended to\nother power converters. The purpose of this work is to study how many bits are necessary in order to\navoid the loss of information, but also without wasting bits. Errors of the state variables are obtained\nwith different sizes of feedback signals. These show that the errors in each state variable have similar\npatterns. When the number of bits increases, the error decreases down to a certain number of bits,\nwhere an almost constant error appears. However, when the bits decrease, the error increases linearly.\nFurthermore, the results show that there is a direct relation between the number of bits in feedback\nsignals and the inputs of the converter in the global error. Finally, a design criterion is given to choose\nthe optimum width for each feedback signal, without wasting bits.
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